External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

13.7.2.4.8. Pin Delay Settings Tab

The Pin Delay Settings tab lets you view and change delay values on specific pins.

You can select the Pin Type, Pin ID, Rank, or Direction values of a delay that you are interested in, and the toolkit displays the delay value in the Delay Setting (taps) field.

Figure 150. Pin Delay Settings Tab

If you make changes to Delay Setting (taps) tab, the delay value is updated in hardware. After the value changes in hardware and no longer matches the setting found in calibration, a warning message appears, indicating that the margins in the Calibration tab are out-of-date.

Figure 151. Error Message Resulting from Changed Delay Settings

To restore the delay settings to the values found during the most recent calibration, click the Restore Delay Settings button on the Pin Delay Settings tab.

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