External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022

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Document Table of Contents Communication

Communication between the EMIF Toolkit and external memory interface connections is achieved using a JTAG Avalon® -MM master attached to the sequencer bus.

The following figure shows the structure of EMIF IP with JTAG Avalon® -MM master attached to sequencer bus masters.

Figure 111. EMIF IP with JTAG Avalon-MM Master