External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Download
ID 683741
Date 3/11/2022
Public
Document Table of Contents

13.7.1.2. Communication

Communication between the EMIF Toolkit and external memory interface connections is achieved using a JTAG Avalon® -MM master attached to the sequencer bus.

The following figure shows the structure of EMIF IP with JTAG Avalon® -MM master attached to sequencer bus masters.

Figure 111. EMIF IP with JTAG Avalon-MM Master


Did you find the information on this page useful?

Characters remaining:

Feedback Message