External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.4.1. Including the Legacy Efficiency Monitor and Protocol Checker in Your Generated IP

To include the Legacy Efficiency Monitor and Protocol Checker when you generate your IP, follow these steps.
On the Diagnostics tab of the parameter editor, turn on Enable the Efficiency Monitor.
  • If you want to see the results compiled by the Efficiency Monitor using the EMIF Debug Toolkit, select Interface to EMIF Debug Toolkit.
  • If you want to communicate directly to the Efficiency Monitor, select Export. (Refer to Communicating Directly to the Efficiency Monitor and Protocol Checker for a memory map of registers within the Efficiency Monitor and Protocol Checker.)
Figure 158. Enabling the Legacy Efficiency Monitor and Protocol Checker

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