External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.4.17. emif_usr_clk for QDR-IV

User clock interface

Table 127.  Interface: emif_usr_clkInterface type: Clock Output
Port Name Direction Description
emif_usr_clk Output User clock domain

Did you find the information on this page useful?

Characters remaining:

Feedback Message