External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.3.1.1. Estimating Pin Requirements

You should use the Intel® Quartus® Prime software for final pin fitting. However, you can estimate whether you have enough pins for your memory interface using the EMIF Device Selector on www.altera.com, or perform the following steps:
  1. Determine how many read/write data pins are associated per data strobe or clock pair.
  2. Calculate the number of other memory interface pins needed, including any other clocks (write clock or memory system clock), address, command, and RZQ. Refer to the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired configuration.
  3. Calculate the total number of I/O banks required to implement the memory interface, given that an I/O bank supports up to 48 GPIO pins.

You should test the proposed pin-outs with the rest of your design in the Intel® Quartus® Prime software (with the correct I/O standard and OCT connections) before finalizing the pin-outs. There can be interactions between modules that are illegal in the Intel® Quartus® Prime software that you might not know about unless you compile the design and use the Intel® Quartus® Prime Pin Planner.

Did you find the information on this page useful?

Characters remaining:

Feedback Message