External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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8.4.4. QDR II SRAM Layout Approach

Using the layout guidelines in the above table, Intel recommends the following layout approach:
  1. Route the K/K# clocks and set the clocks as the target trace propagation delays for the output signal group.
  2. Route the write data output signal group (write data, byte write select), ideally on the same layer as the K/K# clocks, to within ±10 ps skew of the K/K# traces.
  3. Route the address/control output signal group (address, RPS, WPS), ideally on the same layer as the K/K# clocks, to within ±20 ps skew of the K/K# traces.
  4. Route the CQ/CQ# clocks and set the clocks as the target trace propagation delays for the input signal group.
  5. Route the read data output signal group (read data), ideally on the same layer as the CQ/CQ# clocks, to within ±10 ps skew of the CQ/CQ# traces.
  6. The output and input groups do not need to have the same propagation delays, but they must have all the signals matched closely within the respective groups.
Note: Intel recommends that you create your project with a fully implemented external memory interface, and observe the interface timing margins to determine the actual margins for your design.

Although the recommendations in this section are based on simulations, you can apply the same general principles when determining the best termination scheme, drive strength setting, and loading style to any board designs. Even armed with this knowledge, it is still critical that you perform simulations, either using IBIS or HSPICE models, to determine the quality of signal integrity on your designs.

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