External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022

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13.9.3. Default Traffic Pattern

The traffic generator's default traffic pattern consists of three stages, which run sequentially.

If you select the Enable default traffic pattern parameter, the following three traffic stages run when the traffic generator comes out of the reset state:

Table 357.  
Traffic Stage Description
Single RW stage The traffic generator sends a single write instruction, followed by a single read instruction, and compares the results. This loop of a single write followed by a single read is issued three times.
Block RW stage The traffic generator sends a block of write instructions followed by the same number of read instructions—this sequence is called a loop. The number of loops performed, as well as the number of writes and reads performed within each loop, is determined by the value that you choose for the TG2 test duration parameter.

The traffic generator executes this stage once for each of the three address modes (Sequential, Random, and Random-Sequential).

Byte-enable stage
  • The traffic generator randomly generates a byte-enable value and performs a block of writes to a start address, in Sequential Address Mode.
  • The traffic generator then uses the inverted write and inverted byte-enable value, and performs a second block of writes, starting at the same address.
  • Finally, the traffic generator issues reads from the same start address with all bytes enabled, and compares the read data to the write data and inverted write data, where applicable.

To run the default traffic pattern, the traffic generator uses the same infrastructure as the user-configured traffic stage; that is, for each part of the default traffic pattern, the traffic generator sets the configuration registers to pre-set default values. The registers used to configure this traffic pattern are described in more detail in the User-Configured Traffic Pattern topic.