External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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10.1.3. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Memory

Table 329.  Group: Memory / Topology
Display Name Description
DQ width per device Specifies number of DQ pins per RLDRAM3 device. Available widths for DQ are x18 and x36. (Identifier: MEM_RLD3_DQ_PER_DEVICE)
Enable DM pins Indicates whether the interface uses the DM pins. If enabled, one DM pin per write data group is added. (Identifier: MEM_RLD3_DM_EN)
Enable width expansion Indicates whether to combine two memory devices to double the data bus width. With two devices, the interface supports a width expansion configuration up to 72-bits. For width expansion configuration, the address and control signals are routed to 2 devices. (Identifier: MEM_RLD3_WIDTH_EXPANDED)
Enable depth expansion using twin die package Indicates whether to combine two RLDRAM3 devices to double the address space, resulting in more density. (Identifier: MEM_RLD3_DEPTH_EXPANDED)
Address width Number of address pins. (Identifier: MEM_RLD3_ADDR_WIDTH)
Bank address width Number of bank address pins (Identifier: MEM_RLD3_BANK_ADDR_WIDTH)
Table 330.  Group: Memory / Mode Register Settings
Display Name Description
tRC Determines the mode register setting that controls the tRC(activate to activate timing parameter). Refer to the tRC table in the memory vendor data sheet. Set the tRC according to the memory speed grade and data latency. (Identifier: MEM_RLD3_T_RC_MODE_ENUM)
Data Latency Determines the mode register setting that controls the data latency. Sets both READ and WRITE latency (RL and WL). (Identifier: MEM_RLD3_DATA_LATENCY_MODE_ENUM)
Output drive Determines the mode register setting that controls the output drive setting. (Identifier: MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM)
ODT Determines the mode register setting that controls the ODT setting. (Identifier: MEM_RLD3_ODT_MODE_ENUM)
AREF protocol Determines the mode register setting that controls the AREF protocol setting. The AUTO REFRESH (AREF) protocol is selected by setting mode register 1. There are two ways in which AREF commands can be issued to the RLDRAM, the memory controller can either issue bank address-controlled or multibank AREF commands. Multibank refresh protocol allows for the simultaneous refreshing of a row in up to four banks (Identifier: MEM_RLD3_AREF_PROTOCOL_ENUM)
Burst length Determines the mode register setting that controls the burst length. (Identifier: MEM_RLD3_BL)
Write protocol Determines the mode register setting that controls the write protocol setting. When multiple bank (dual bank or quad bank) is selected, identical data is written to multiple banks. (Identifier: MEM_RLD3_WRITE_PROTOCOL_ENUM)

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