External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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9.4.2. General Layout Guidelines

The following table lists general board design layout guidelines. These guidelines are Intel® recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface. You should extract the propagation delay information, enter it into the IP and compile the design to ensure that timing requirements are met.
Table 252.  Table 285.  Table 316.  Table 345.  General Layout Guidelines

Parameter

Guidelines

Impedance

  • All unused via pads must be removed, because they cause unwanted capacitance.
  • Trace impedance plays an important role in the signal integrity. You must perform board level simulation to determine the best characteristic impedance for your PCB. For example, it is possible that for multi rank systems 40 ohms could yield better results than a traditional 50 ohm characteristic impedance.

Decoupling Parameter

  • Use 0.1 uF in 0402 size to minimize inductance
  • Make VTT voltage decoupling close to termination resistors
  • Connect decoupling caps between VTT and ground
  • Use a 0.1 uF cap for every other VTT pin and 0.01 uF cap for every VDD and VDDQ pin
  • Verify the capacitive decoupling using the Intel® Power Distribution Network Design Tool

Power

  • Route GND and VCC as planes
  • Route VCCIO for memories in a single split plane with at least a 20-mil (0.020 inches, or 0.508 mm) gap of separation
  • Route VTT as islands or 250-mil (6.35-mm) power traces
  • Route oscillators and PLL power as islands or 100-mil (2.54‑mm) power traces

General Routing

All specified delay matching requirements include PCB trace delays, different layer propagation velocity variance, and crosstalk. To minimize PCB layer propagation variance, Intel® recommends that signals from the same net group always be routed on the same layer.

  • Use 45° angles (not 90° corners)
  • Avoid T-Junctions for critical nets or clocks
  • Avoid T-junctions greater than 250 mils (6.35 mm)
  • Disallow signals across split planes
  • Restrict routing other signals close to system reset signals
  • Avoid routing memory signals closer than 0.025 inch (0.635 mm) to PCI or system clocks

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