External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.5.5. Operate at a Lower Speed

Test the interface at a lower speed. If the interface works at a lower speed, the interface is correctly pinned out and functional.

If the interface fails at a lower speed, determine if the test is valid. Many high-speed memory components have a minimal operating frequency, or require subtly different configurations when operating at a lower speeds.

For example, DDR3 SDRAM typically requires modification to the following parameters if you want to operate the interface at lower speeds:

  • tMRD
  • tWTR
  • CAS latency and CAS write latency

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