External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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9.3.1.5. PLL

When using PLL for external memory interfaces, you must consider the following guidelines:
  • For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. If the clock source for the PLL is not a dedicated clock input pin for the dedicated PLL, you would need an additional clock network to connect the clock source to the PLL block. Using additional clock network may increase clock jitter and degrade the timing margin.
  • Pick a PLL and PLL input clock pin that are located on the same side of the device as the memory interface pins.
  • Share the DLL and PLL static clocks for multiple memory interfaces provided the controllers are on the same or adjacent side of the device and run at the same memory clock frequency.
  • If your design uses a dedicated PLL to only generate a DLL input reference clock, you must set the PLL mode to No Compensation in the Intel® Quartus® Prime software to minimize the jitter, or the software forces this setting automatically. The PLL does not generate other output, so it does not need to compensate for any clock path.

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