External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.1.8. Intel Stratix 10 EMIF IP DDR4 Parameters: Diagnostics

Table 239.  Group: Diagnostics / Simulation Options
Display Name Description
Calibration mode Specifies whether to skip memory interface calibration during simulation, or to simulate the full calibration process.

Simulating the full calibration process can take hours (or even days), depending on the width and depth of the memory interface. You can achieve much faster simulation times by skipping the calibration process, but that is only expected to work when the memory model is ideal and the interconnect delays are zero.

If you enable this parameter, the interface still performs some memory initialization before starting normal operations. Abstract PHY is supported with skip calibration.

(Identifier: DIAG_DDR4_SIM_CAL_MODE_ENUM)
Abstract phy for fast simulation Specifies that the system use Abstract PHY for simulation. Abstract PHY replaces the PHY with a model for fast simulation and can reduce simulation time by 3-10 times. Abstract PHY is available for certain protocols and device families, and only when you select Skip Calibration. (Identifier: DIAG_DDR4_ABSTRACT_PHY)
Show verbose simulation debug messages This option allows adjusting the verbosity of the simulation output messages. (Identifier: DIAG_DDR4_SIM_VERBOSE)
Table 240.  Group: Diagnostics / Calibration Debug Options
Display Name Description
Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.

Only one EMIF debug interface should be instantiated per I/O column. You can chain additional EMIF or PHYLite cores to the first by enabling the "Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export" for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option on all cores after the first.

(Identifier: DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE)
Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies that the IP export an Avalon-MM master interface (cal_debug_out) which can connect to the cal_debug interface of other EMIF cores residing in the same I/O column. This parameter applies only if the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer to the Debugging Multiple EMIFs wiki page for more information about debugging multiple EMIFs. (Identifier: DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER)
First EMIF Instance in the Avalon Chain If selected, this EMIF instance will be the head of the Avalon interface chain connected to the master. For simulation purposes it is needed to identify the first EMIF instance in the avalon Chain. (Identifier: DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN)
Interface ID Identifies interfaces within the I/O column, for use by the EMIF Debug Toolkit and the On-Chip Debug Port. Interface IDs should be unique among EMIF cores within the same I/O column. If the Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port parameter is set to Disabled, the interface ID is unused. (Identifier: DIAG_DDR4_INTERFACE_ID)
Skip address/command leveling calibration Specifies to skip the address/command leveling stage during calibration. Address/command leveling attempts to center the memory clock edge against CS# by adjusting delay elements inside the PHY, and then applying the same delay offset to the rest of the address and command pins. (Identifier: DIAG_DDR4_SKIP_CA_LEVEL)
Skip address/command deskew calibration Specifies to skip the address/command deskew calibration stage. Address/command deskew performs per-bit deskew for the address and command pins. (Identifier: DIAG_DDR4_SKIP_CA_DESKEW)
Skip VREF calibration Specifies to skip the VREF stage of calibration. Enable this parameter for debug purposes only; generally, you should include the VREF calibration stage during normal operation. (Identifier: DIAG_DDR4_SKIP_VREF_CAL)
Use Soft NIOS Processor for On-Chip Debug Enables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option. (Identifier: DIAG_SOFT_NIOS_MODE)
Table 241.  Group: Diagnostics / Example Design
Display Name Description
Number of core clocks sharing slaves to instantiate in the example design Specifies the number of core clock sharing slaves to instantiate in the example design. This parameter applies only if you set the "Core clocks sharing" parameter in the "General" tab to "Master" or "Slave". (Identifier: DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES)
Enable In-System-Sources-and-Probes Enables In-System-Sources-and-Probes in the example design for common debug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do driver margining using the EMIF Debug Toolkit. (Identifier: DIAG_DDR4_EX_DESIGN_ISSP_EN)
Table 242.  Group: Diagnostics / Traffic Generator (settings only applicable for example design)
Display Name Description
Use configurable Avalon traffic generator 2.0 This option allows users to add the new configurable Avalon traffic generator to the example design. (Identifier: DIAG_DDR4_USE_TG_AVL_2)
Enable default traffic pattern (pattern configured during compile-time) Specifies that the default traffic pattern will be enabled. If this parameter is enabled, a default traffic pattern will be run immediately every time the traffic generator comes out of reset. If this parameter is disabled, the traffic generator will not run any traffic until it is signaled to start by its Avalon configuration interface.
Enable user-configured traffic pattern (pattern configured during run-time) Specifies that the user-defined traffic pattern will be enabled. If this parameter is enabled, the traffic generator will respond to the configuration interface and launch a user-configured traffic pattern when signaled to. If this parameter is disabled, the traffic generator will ignore commands on the configuration interface and will not run any user-defined traffic..
TG2 default traffic duration This option allows adjusting the pattern length of default (compile-time) traffic.
TG2 Configuration Interface Mode Specifies the connectivity of an Avalon slave interface for use by the TG Configuration Toolkit or user core logic. If you set this parameter to Export, an Avalon slave interface named tg_cfg is exported from the IP. If you select JTAG, a JTAG Avalon Master Endpoint is connected to the configuration interface, allowing the core to be accessed by the TG Configuration Toolkit.
Table 243.  Group: Diagnostics / Performance
Display Name Description
Enable Efficiency Monitor Adds an Efficiency Monitor component to the Avalon-MM interface of the memory controller, allowing you to view efficiency statistics of the interface. You can access the efficiency statistics using the EMIF Debug Toolkit. (Identifier: DIAG_DDR4_EFFICIENCY_MONITOR)
Use Efficiency Monitor with Unified Toolkit Specifies the efficiency monitor version to be used. The new efficiency monitor works with the Unified Toolkit.
Table 244.  Group: Diagnostics / Miscellaneous
Display Name Description
Export PLL lock signal Specifies whether to export the pll_locked signal at the IP top-level to indicate status of PLL. (Identifier: DIAG_EXPORT_PLL_LOCKED)
Export Address/Command parity error indicator Specifies whether to export the ac_parity_err interface at the IP top level to indicate if a parity error was detected on the Address/Command bus by the memory, causing ALERT_N to toggle. To enable this option, the ADDR/CMD parity latency option must not be set to Disabled.

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