External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.4.2. ctrlcfg1

address=11(32 bit)

Field Bit High Bit Low Description Access
Reserved 4 0 Reserved. Read
cfg_addr_order 6 5 Indicates the order for address interleaving. This is related to mappings between Avalon-MM address and the SDRAM address. "00" - chip, row, bank(BG, BA), column; "01" - chip, bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column. Read
cfg_ctrl_enable_ecc 7 7 Enable the generation and checking of ECC. Read
cfg_dbc0_enable_ecc 8 8 Enable the generation and checking of ECC. Read
cfg_dbc1_enable_ecc 9 9 Enable the generation and checking of ECC. Read
cfg_dbc2_enable_ecc 10 10 Enable the generation and checking of ECC. Read
cfg_dbc3_enable_ecc 11 11 Enable the generation and checking of ECC. Read
cfg_reorder_data 12 12 This bit controls whether the controller can reorder operations to optimize SDRAM bandwidth. It should generally be set to a one. Read
cfg_ctrl_reorder_rdata 13 13 This bit controls whether the controller needs to reorder the read return data. Read
cfg_dbc0_reorder_rdata 14 14 This bit controls whether the controller needs to reorder the read return data. Read
cfg_dbc1_reorder_rdata 15 15 This bit controls whether the controller needs to reorder the read return data. Read
cfg_dbc2_reorder_rdata 16 16 This bit controls whether the controller needs to reorder the read return data. Read
cfg_dbc3_reorder_rdata 17 17 This bit controls whether the controller needs to reorder the read return data. Read
cfg_reorder_read 18 18 This bit controls whether the controller can reorder read command. Read
cfg_starve_limit 24 19 Specifies the number of DRAM burst transactions that an individual transaction allows to reorder ahead of it before its priority is raised in the memory controller. Read
Reserved 25 25 Reserved. Read
cfg_ctrl_enable_dm 26 26 Set to 1 to enable DRAM operation if DM pins are connected. Read
cfg_dbc0_enable_dm 27 27 Set to 1 to enable DRAM operation if DM pins are connected. Read
cfg_dbc1_enable_dm 28 28 Set to 1 to enable DRAM operation if DM pins are connected. Read
cfg_dbc2_enable_dm 29 29 Set to 1 to enable DRAM operation if DM pins are connected. Read
cfg_dbc3_enable_dm 30 30 Set to 1 to enable DRAM operation if DM pins are connected. Read

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