External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.1.32. ctrl_ecc_status for DDR3

Controller ECC status interface

Table 43.  Interface: ctrl_ecc_statusInterface type: Conduit
Port Name Direction Description
ctrl_ecc_sts_intr Output ECC interrupt status - '1' indicates interrupt occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_sbe_error Output '1' indicates SBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_dbe_error Output '1' indicates DBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_corr_dropped Output Correction command dropped status, '1' indicates correction command dropped; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_sbe_count Output Number of times SBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_dbe_count Output Number of times DBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_corr_dropped_count Output Number of times correction command dropped; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_err_addr Output Address of the most recent SBE or DBE; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB
ctrl_ecc_sts_corr_dropped_addr Output Address of the most recent correction command dropped; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB

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