External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.3.3. AFI Read Sequence Timing Diagrams

The following waveforms illustrate the AFI read data waveform in full, half, and quarter-rate, respectively.

The afi_rdata_en_full signal must be asserted for the entire read burst operation. The afi_rdata_en signal need only be asserted for the intended read data.

Aligned and unaligned access for read commands is similar to write commands; however, the afi_rdata_en_full signal must be sent on the same memory clock in a PHY clock as the read command. That is, if a read command is sent on the second memory clock in a PHY clock, afi_rdata_en_full must also be asserted, starting from the second memory clock in a PHY clock.

Figure 38. AFI Read Data Full-Rate

The following figure illustrates that the second and third reads require only the first and second half of data, respectively. The first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.

Figure 39. AFI Read Data Half-Rate

In the following figure, the first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.

Figure 40. AFI Read Data Quarter-Rate

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