External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.5.3. Control and Status Registers

Status registers hold a record of the transactions that happen on the Avalon® interface and contain useful information for the efficiency calculation. You can enable, disable, or reset the recording of transactions on the status registers, through the control registers.

The following table summarizes the available registers.

Table 355.  Control and Status Registers
Symbol Address Register Name Readable or Writeable Register Description
0x0 EFFMON_START Readable and Writeable
  • Write a value of 1 to enable the Efficiency Monitor.
  • Write a value of 0 to disable the Efficiency Monitor.
0x4 EFFMON_READ_COUNTER Readable Number of read commands issued.
0x8 EFFMON_WRITE_COUNTER Readable Number of write commands issued.
0xC EFFMON_CYCLE_COUNTER Readable Number of clock cycles after the first command (read or write) issued on the interface. (This counter stops at EFFMON_CYCLE_COUNTER_MAX.)
0x10 EFFMON_COUNTER_SATURATION Readable
  • A value of 1 indicates that EFFMON_CYCLE_COUNTER has reached EFFMON_CYCLE_COUNTER_MAX, and further data is not collected until all status registers are cleared.
  • A value of 0 indicates the counter has not saturated.
0x14 EFFMON_RDLAT_MIN Readable Minimum read latency. Read latency is measured from the clock cycle at which a read command is issued to the clock cycle where the corresponding readdatavalid signal is asserted.
0x18 EFFMON_RDLAT_MAX Readable Maximum read latency. Read latency is measured from the clock cycle at which a read command is issued to the clock cycle where the corresponding readdatavalid signal is asserted.
0x1C EFFMON_RDLAT_TOTAL_L Readable Total read latency (lower 32 bits). Read Latency is measured from the clock cycle at which a read command is issued to the clock cycle where the corresponding readdatavalid signal is asserted.
0x20 EFFMON_RDLAT_TOTAL_H Readable Total read latency (upper 32 bits). Read Latency is measured from the clock cycle at which a read command is issued to the clock cycle where the corresponding readdatavalid signal is asserted.
0x24 EFFMON_READDATAVALID_COUNTER Readable Total number of clock cycles in which readdatavalid is asserted.
0x28 EFFMON_TRANSFER_COUNTER Readable Indicates the number of cycles where amm_write and amm_ready are asserted or amm_readdatavalid is asserted.
0x2C EFFMON_COMMAND_WAIT_COUNTER Readable Indicates the total number of cycles in which the issuance of a read or write command was stalled due to waitrequest being asserted.
0x30 EFFMON_NO_READDATAVALID_COUNTER Readable Indicates the number of cycles where readdatavalid is low after a read command has been issued.
0x34 EFFMON_MASTER_IDLE_COUNTER Readable Indicates the number of cycles where there is no read or write from the master after the first command (read or write) has been issued on the interface.
0x38 EFFMON_MASTER_WRIDLE_COUNTER Readable Indicates the number of cycles in which the master is unable to provide valid write data and is forced to deassert WRITE within a multi-word burst.
0x3C EFFMON_STATUS_CLEAR Readable and Writeable Write a value of 1 to clear all the status registers. (This value is set back to 0 automatically, after the status registers are cleared.)
0x40 EFFMON_CYCLE_COUNTER_SNAPSHOT Readable Stores a snapshot of EFFMON_CYCLE_COUNTER, as it was at the time of the last transaction on the interface (such as a read, a write, or a read_data_valid). This is the value used as the denominator for efficiency calculations in the toolkit GUI.

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