External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Download
ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.4.4. pll_locked for QDR-IV

PLL locked signal

Table 114.  Interface: pll_lockedInterface type: Conduit
Port Name Direction Description
pll_locked Output PLL lock signal to indicate whether the PLL has locked

Did you find the information on this page useful?

Characters remaining:

Feedback Message