External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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6.4.3.6. Resource Sharing Guidelines (Multiple Interfaces)

In the external memory interface IP, different external memory interfaces can share PLL reference clock pins, core clock networks, I/O banks, and hard Nios® processors. Each I/O bank has DLL and PLL resources, therefore these do not need to be shared. The Intel® Quartus® Prime Fitter automatically merges DLL and PLL resources when a bank is shared by different external memory interfaces, and duplicates them for a multi-I/O-bank external memory interface.

PLL Reference Clock Pin

To conserve pin usage and enable core clock network and I/O bank sharing, you can share a PLL reference clock pin between multiple external memory interfaces; the interfaces must be of the same protocol, rate, and frequency. Sharing of a PLL reference clock pin also implies sharing of the reference clock network.

Observe the following guidelines for sharing the PLL reference clock pin:

  1. To share a PLL reference clock pin, connect the same signal to the pll_ref_clk port of multiple external memory interfaces in the RTL code.
  2. Place related external memory interfaces in the same I/O column.
  3. Place related external memory interfaces in adjacent I/O banks. If you leave an unused I/O bank between the I/O banks used by the external memory interfaces, that I/O bank cannot be used by any other external memory interface with a different PLL reference clock signal.
Note: You can place the pll_ref_clk pin in the address and command I/O bank or in a data I/O bank, there is no impact on timing. However, for greatest flexibility during debug (such as when creating designs with narrower interfaces), the recommended placement is in the address and command I/O bank.

Core Clock Network

To access all external memory interfaces synchronously and to reduce global clock network usage, you may share the same core clock network with other external memory interfaces.

Observe the following guidelines for sharing the core clock network:

  1. To share a core clock network, connect the clks_sharing_master_out of the master to the clks_sharing_slave_in of all slaves in the RTL code.
  2. Place related external memory interfaces in the same I/O column.
  3. Related external memory interface must have the same rate, memory clock frequency, and PLL reference clock.

I/O Bank

To reduce I/O bank utilization, you may share an I/O Bank with other external memory interfaces.

Observe the following guidelines for sharing an I/O Bank:

  1. Related external memory interfaces must have the same protocol, rate, memory clock frequency, and PLL reference clock.
  2. You cannot use a given I/O bank as the address and command bank for more than one external memory interface.
  3. You cannot share an I/O lane between external memory interfaces, but an unused pin can serve as a general purpose I/O pin, of compatible voltage and termination standards.

Hard Nios® Processor

All external memory interfaces residing in the same I/O column share the same hard Nios® processor. The shared hard Nios® processor calibrates the external memory interfaces serially.

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