External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
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13.9.5.1. Test Duration / Instruction pattern

In the traffic generator, a loop refers to a set of writes followed by a set of reads.

Example test pattern:

TG_LOOP_COUNT=2     TG_WRITE_REPEAT_COUNT=1     TG_RW_GEN_IDLE_COUNT=0
TG_WRITE_COUNT=3     TG_READ_REPEAT_COUNT=1     TG_RW_GEN_LOOP_IDLE_COUNT=4
TG_READ_COUNT=3     TG_BURST_LENGTH=2
Figure 171. Timing Diagram for Example Test Pattern

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