External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7. Debugging Intel® Stratix® 10 EMIF IP

You can debug hardware failures by connecting to the Legacy EMIF Debug Toolkit or the EMIF Unified Calibration Debug Toolkit, or by exporting an Avalon® -MM slave port, from which you can access information gathered during calibration. You can also connect to this port to mask ranks and to request recalibration.

About the Legacy EMIF Debug Toolkit and the EMIF Unified Calibration Debug Toolkit

Commencing with the Intel® Stratix® 10 EMIF IP version 19.2.1 ( Intel® Quartus® Prime software version 20.2), two debug toolkits are available. In general, the two toolkits offer many similar features, however the Unified Toolkit does not require an installation of the Intel® Quartus® Prime software. In addition, it can read ISSPs and easily rerun the traffic generator.

The following table summarizes the features of the two debug toolkits:

Feature Supported by the Legacy EMIF Debug Toolkit? Supported by the EMIF Unified Calibration Debug Toolkit?
Protocol support All protocols. DDR4 only.
Can run in System Console — no full Intel® Quartus® Prime software required Not supported Yes
Reading Memory Configuration Yes Yes
Reading Data Pin Calibration Margins/delay settings Yes Yes
Reading A/C Margins/delay settings Yes Not supported
Reading Vref margins/settings Yes Yes
Rerunning Calibration Yes Yes
Reading Calibration Status Report Yes Yes
Rerunning traffic generator (through ISSPs) Not supported Yes
Driver Margining Yes Yes
ODT Calibration Yes Yes
Vref Margining Yes Yes
Manually Adjusting Pin Delays Yes Yes
Graphic representations of margins Yes Yes
Reading and Writing to all ISSPs Not supported Yes

Accessing the Exported Avalon® -MM Port

You can access the exported Avalon® -MM port in two ways:

  • Via the External Memory Interface Debug Toolkit
  • Via On-Chip Debug (core logic on the FPGA)

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