External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.5.5.2. Address and Command Deskew

Deskew address and command delays as follows:
  1. Select the FPGA Address/Command Package Skews Deskewed on Board checkbox on the Board Settings tab of the parameter editor.
  2. Generate your IP.
  3. Instantiate your IP in the project.
  4. Compile your design.
  5. Refer to the All Package Pins compilation report, or find the pin delays displayed in the <core_name>.pin file.

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