126.96.36.199. Hard Memory Controller Features
|Memory standards support||
Supports the following memory standards:
|Memory devices support||Supports the following memory devices:
|3D Stacked Die support||Supports 2 and 4 height of 3D stacked die for DDR4 to increase memory capacity.|
|Memory controller bypass mode||You can use this configurable mode to bypass the hard memory controller and use your own customized controller.|
|Ping-Pong controller mode||You can use this configurable mode to enable two memory controllers to time-share the same set of address and command pins.|
|Interface protocols support||
|Rate support||The hard memory controller runs at half rate. It can accept memory access commands from the core logic at half rate or quarter rate.|
|Configurable memory interface width||Supports data widths from 8 to 72 bits, in 8 bit increments|
|Multiple ranks support||Supports:
Able to accept burst lengths of 1–127 on the local interface of the controller and map the bursts to efficient memory commands. For applications that must strictly adhere to the Avalon® -MM specification, the maximum burst length is 64.
No burst chop support for DDR3 and DDR4.
|Efficiency optimization features||
|User requested priority||You can assign priority to commands. This feature allows you to specify that higher priority commands are issued earlier to reduce latency.|
|Starvation counter||Ensures all requests are served after a predefined time out period, which ensures that low priority access are not left behind while reordering data for efficiency.|
|Timing for address/command bus||
To maximize command bandwidth, you can double the number of memory commands in one controller clock cycle:
Note: Quasi-1T and Quasi-2T addressing is not supported for Ping Pong PHY.
|Bank interleaving||Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses.|
|On-die termination||The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.|
|DQS tracking||Tracks the DQS timing and makes auto adjustments to align to the DQS edges.|
|Power saving features||
|Mode register set||Access the memory mode register.|
|User ZQ calibration||Long or short ZQ calibration request for DDR3 or DDR4.|
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