External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.2.4.3. Calibration Report Tab

The Calibration Report tab shows the calibration status, as well as delay settings and margins discovered during calibration.

Choose the Iteration to View

You may choose to view the status, delay settings, or margins reports for any of the most recent calibration iterations (which were initiated through the toolkit). To choose the iteration to view, select from the Iteration to Display dropdown.

Figure 135. Selecting the Iteration to Display

ODT Settings in Effect

This report shows the current ODT settings for the latest calibration.

Figure 136. ODT Settings in Effect

Calibration Status Report

The Calibration Status report shows the calibration status and memory parity (ALERT_N) status. If a failure occurs, this report shows the first stage of calibration that failed, as well as which data groups failed this stage. Memory parity status observed during calibration is shown for DDR4 interfaces if you have enabled ISSPs in the design. The calibration status report window includes a memory parity status LED and a button that allows you to reread the memory parity status.

Figure 137. Calibration Status

Calibration Delays and Margins Reports

The Calibration Delays and Margins reports provide detailed information about the margins observed during calibration, and the settings applied on the calibration bus during calibration. To view the margins, click on the respective section for DQ, DQS, DM_DBI, VREF or Address and Command.

Figure 138. DQ Calibration Delays and Margins

Figure 139. DQS Calibration Delays and Margins

Figure 140. DM_DBI Calibration Delays and Margins

Figure 141. VREF Calibration Settings

Figure 142. Address and Command Calibration Delays and Margins

Note: Reports can also be viewed graphically; for information, refer to Viewing Diagrams in Eye Viewer .

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