External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

7.5.4.8. Additional Layout Guidelines for DDR4 Twin-die Devices

Twin-die DDR4 memory devices have increased capacitive loading on the address, command, and memory clock signals, which can affect the signal integrity in a fly-by topology.

To ensure a good PCB layout, you should perform board-level simulations to optimize the fly-by topology, trace impedance, and terminations. The following techniques may help you improve signal integrity:

  • Fly-by component placement: Compact layouts such as clamshell topologies tend to cause worse reflections. To reduce reflections at the first DRAM, add some additional signal routing between the first and second DRAMs, relative to the other fly-by routing lengths.
  • PCB trace impedance: You may reduce reflections by increasing the trace impedance from the first to the last DRAM. However, be aware that thinner traces may cause issues with PCB fabrication.
  • Board simulation models: Verify the IBIS model correlation accuracy with your memory vendor and determine whether package loss is modeled. HSPICE simulation models might be more accurate.
  • Terminations: Experiment with different values of the parallel termination to Vtt.

If you encounter memory test errors during hardware testing and suspect problems with address and command signal integrity, you can confirm the address and command signal integrity as follows:

  • Probe the alert_n signal with an oscilloscope and look for a falling edge after the memory has calibrated. A parity error on the address and command signals causes alert_n to pulse low.

Did you find the information on this page useful?

Characters remaining:

Feedback Message