External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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10.1.4. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 331.  Group: Mem Timing
Display Name Description
Speed bin The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run. (Identifier: MEM_RLD3_SPEEDBIN_ENUM)
tDS (base) tDS(base) refers to the setup time for the Data (DQ) bus before the rising edge of the DQS strobe. (Identifier: MEM_RLD3_TDS_PS)
tDS (base) AC level tDS (base) AC level refers to the voltage level which the data bus must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period. (Identifier: MEM_RLD3_TDS_AC_MV)
tDH (base) tDH (base) refers to the hold time for the Data (DQ) bus after the rising edge of CK. (Identifier: MEM_RLD3_TDH_PS)
tDH (base) DC level tDH (base) DC level refers to the voltage level which the data bus must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period. (Identifier: MEM_RLD3_TDH_DC_MV)
tQKQ_max tQKQ_max describes the maximum skew between the read strobe (QK) clock edge to the data bus (DQ/DINV) edge. (Identifier: MEM_RLD3_TQKQ_MAX_PS)
tQH tQH specifies the output hold time for the DQ/DINV in relation to QK. (Identifier: MEM_RLD3_TQH_CYC)
tCKDK_max tCKDK_max refers to the maximum skew from the memory clock (CK) to the write strobe (DK). (Identifier: MEM_RLD3_TCKDK_MAX_CYC)
tCKDK_min tCKDK_min refers to the minimum skew from the memory clock (CK) to the write strobe (DK). (Identifier: MEM_RLD3_TCKDK_MIN_CYC)
tCKQK_max tCKQK_max refers to the maximum skew from the memory clock (CK) to the read strobe (QK). (Identifier: MEM_RLD3_TCKQK_MAX_PS)
tIS (base) tIS (base) refers to the setup time for the Address/Command/Control (A) bus to the rising edge of CK. (Identifier: MEM_RLD3_TIS_PS)
tIS (base) AC level tIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period. (Identifier: MEM_RLD3_TIS_AC_MV)
tIH (base) tIH (base) refers to the hold time for the Address/Command (A) bus after the rising edge of CK. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user chooses the "tIH (base) AC level"). (Identifier: MEM_RLD3_TIH_PS)
tIH (base) DC level tIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period. (Identifier: MEM_RLD3_TIH_DC_MV)

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