3.1.3. Intel® Stratix® 10 EMIF Architecture: I/O SSM
The I/O SSM includes dedicated memory which stores both the calibration algorithm and calibration run-time data. The hardened Nios II processor and the dedicated memory can be used only by an external memory interface, and cannot be employed for any other use. The I/O SSM can interface with soft logic, such as the debug toolkit, via an Avalon-MM bus.
The I/O SSM is clocked by an on-die oscillator, and therefore does not consume a PLL.
Did you find the information on this page useful?