10.4. RLDRAM 3 Board Design Guidelines
The following topics focus on the following key factors that affect signal integrity:
- I/O standards
- RLDRAM 3 configurations
- Signal terminations
- Printed circuit board (PCB) layout guidelines
RLDRAM 3 interface signals use the following JEDEC* I/O signaling standards: HSTL 1.2 V and SSTL-12.
The RLDRAM 3 IP defaults to HSTL 1.2 V Class I outputs and HSTL 1.2 V inputs.
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