External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.2.5. pll_extra_clk_0 for DDR4

Additional core clock 0

Table 53.  Interface: pll_extra_clk_0Interface type: Clock Output
Port Name Direction Description
pll_extra_clk_0 Output PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains.

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