External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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6.1.4. Intel Stratix 10 EMIF IP DDR3 Parameters: Mem I/O

Table 186.  Group: Mem I/O / Memory I/O Settings
Display Name Description
Output drive strength setting Specifies the output driver impedance setting at the memory device. To obtain optimum signal integrity performance, select option based on board simulation results. (Identifier: MEM_DDR3_DRV_STR_ENUM)
ODT Rtt nominal value Determines the nominal on-die termination value applied to the DRAM. The termination is applied any time that ODT is asserted. If you specify a different value for RTT_WR, that value takes precedence over the values mentioned here. For optimum signal integrity performance, select your option based on board simulation results. (Identifier: MEM_DDR3_RTT_NOM_ENUM)
Dynamic ODT (Rtt_WR) value Specifies the mode of the dynamic on-die termination (ODT) during writes to the memory device (used for multi-rank configurations). For optimum signal integrity performance, select this option based on board simulation results. (Identifier: MEM_DDR3_RTT_WR_ENUM)
Table 187.  Group: Mem I/O / ODT Activation
Display Name Description
Use Default ODT Assertion Tables Enables the default ODT assertion pattern as determined from vendor guidelines. These settings are provided as a default only; you should simulate your memory interface to determine the optimal ODT settings and assertion patterns. (Identifier: MEM_DDR3_USE_DEFAULT_ODT)

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