External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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6.5.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity

Address and Command ISI and Crosstalk

Simulate the address/command and control signals and capture eye at the DRAM pins, using the memory clock as the trigger for the memory interface's address/command and control signals. Measure the setup and hold channel losses at the voltage thresholds mentioned in the memory vendor's data sheet.

Address and command channel loss = Measured loss on the setup side + measured loss on the hold side.

VREF = VDD/2 = 0.75 V for DDR3

You should select the VIH and VIL voltage levels appropriately for the DDR3L memory device that you are using. Check with your memory vendor for the correct voltage levels, as the levels may vary for different speed grades of device.

The following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is +/- 150 mV and VIH(DC)/ VIL(DC) is +/- 100 mV.

Figure 49. 

Write DQ ISI and Crosstalk

Simulate the write DQ signals and capture eye at the DRAM pins, using DQ Strobe (DQS) as a trigger for the DQ signals of the memory interface simulation. Measure the setup and hold channel losses at the VIH and VIL mentioned in the memory vendor's data sheet. The following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is +/- 150 mV and VIH(DC)/ VIL(DC) is +/- 100 mV.

Write Channel Loss = Measured Loss on the Setup side + Measured Loss on the Hold side

VREF = VDD/2 = 0.75V for DDR3

Figure 50. 

Read DQ ISI and Crosstalk

Simulate read DQ signals and capture eye at the FPGA die. Do not measure at the pin, because you might see unwanted reflections that could create a false representation of the eye opening at the input buffer of the FPGA. Use DQ Strobe (DQS) as a trigger for the DQ signals of your memory interface simulation. Measure the eye opening at +/- 70 mV (VIH/VIL) with respect to VREF.

Read Channel Loss = (UI) - (Eye opening at +/- 70 mV with respect to VREF)

UI = Unit interval. For example, if you are running your interface at 800 Mhz, the effective data is 1600 Mbps, giving a unit interval of 1/1600 = 625 ps

VREF = VDD/2 = 0.75 V for DDR3

Figure 51. 

Write/Read DQS ISI and Crosstalk

Simulate the Write/Read DQS and capture eye, and measure the uncertainty at VREF.

VREF = VDD/2 = 0.75 V for DDR3

Figure 52. 

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