External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.9.5.2.3. Address Generator Effective Width

The effective address width is the number of address bits that are controlled by the 6 address generators.

The effective address width is limited by three parameters and can be calculated as follows:

effective_width = wordAddrWidth - log2(wordAddrDivBy) - ceil_log2(burstlength)

Where:

  • wordAddrWidth is the word address width on the ctrl_amm interface.
  • wordAddrDivBy is the smallest value by which the address on the ctrl_amm interface is divisible to meet the alignment requirement for AMM word address. Generated word address must be divisible by this value. For a half rate (HR) EMIF IP instance without data masking enabled, wordAddrDivBy is 2. In all other cases it is 1.
  • burstlength is the value that you specify in TG_BURST_LENGTH. If not divisible by 2, the ceiling of the log is taken.

Some of the least significant bits (LSBs) of the overall generated address are used implicitly due to AMM protocol requirements. As a result, these LSBs must be tied to zero, which imposes a restriction on the width of field 0 of the address:

field0Width >= log2(wordAddrDivBy) + ceil_log2(burstlength)

If this restriction is not met, the appropriate bit in TG_ERROR_REPORT is set to 1 and data mismatches may occur in the generated traffic pattern (refer to Table 365 for information on error codes).

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