External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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9.1.4. Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 301.  Group: Mem Timing
Display Name Description
Speed bin The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run. (Identifier: MEM_QDR4_SPEEDBIN_ENUM)
tISH tISH provides the setup/hold window requirement for the entire data bus (DK or DINV) in all the data groups with respect to the DK clock. After deskew calibration, this parameter describes the intersection window for all the individual data bus signals setup/hold margins. (Identifier: MEM_QDR4_TISH_PS)
tQKQ_max tQKQ_max describes the maximum skew between the read strobe (QK) clock edge to the data bus (DQ/DINV) edge. (Identifier: MEM_QDR4_TQKQ_MAX_PS)
tQH tQH specifies the output hold time for the DQ/DINV in relation to QK. (Identifier: MEM_QDR4_TQH_CYC)
tCKDK_max tCKDK_max refers to the maximum skew from the memory clock (CK) to the write strobe (DK). (Identifier: MEM_QDR4_TCKDK_MAX_PS)
tCKDK_min tCKDK_min refers to the minimum skew from the memory clock (CK) to the write strobe (DK). (Identifier: MEM_QDR4_TCKDK_MIN_PS)
tCKQK_max tCKQK_max refers to the maximum skew from the memory clock (CK) to the read strobe (QK). (Identifier: MEM_QDR4_TCKQK_MAX_PS)
tASH tASH provides the setup/hold window requirement for the address bus in relation to the CK clock. Because the individual signals in the address bus may not be perfectly aligned with each other, this parameter describes the intersection window for all the individual address signals setup/hold margins. (Identifier: MEM_QDR4_TASH_PS)
tCSH tCSH provides the setup/hold window requirement for the control bus (LD#, RW#) in relation to the CK clock. Because the individual signals in the control bus may not be perfectly aligned with each other, this parameter describes the intersection window for all the individual control signals setup/hold margins. (Identifier: MEM_QDR4_TCSH_PS)

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