## External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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## 10.2.1. Equations for RLDRAM 3 Board Skew Parameters

Table 344.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to device The delay of the longest CK trace from the FPGA to any device.
where n is the number of memory clocks. For example, the maximum CK delay for two pairs of memory clocks is expressed by the following equation:
Maximum DK delay to device The delay of the longest DK trace from the FPGA to any device.
where n is the number of DK. For example, the maximum DK delay for two DK is expressed by the following equation:
Average delay difference between DK and CK

The average delay difference between the DK signals and the CK signal, calculated by averaging the longest and smallest DK delay minus the CK delay. Positive values represent DK signals that are longer than CK signals and negative values represent DK signals that are shorter than CK signals. The Quartus Prime software uses this skew to optimize the delay of the DK signals to have appropriate setup and hold margins.

where n is the number of memory clocks and m is the number of DK.
Maximum system skew within address/command bus
The largest skew between the address and command signals. Enter combined board and package skew.
Average delay difference between address/command and CK The average delay difference between the address and command signals and the CK signal, calculated by averaging the longest and smallest Address/Command signal delay minus the CK delay. Positive values represent address and command signals that are longer than CK signals and negative values represent address and command signals that are shorter than CK signals. The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins.