External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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6.1.5. Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 188.  Group: Mem Timing / Parameters dependent on Speed Bin
Display Name Description
Speed bin The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run. (Identifier: MEM_DDR3_SPEEDBIN_ENUM)
tIS (base) tIS (base) refers to the setup time for the Address/Command/Control (A) bus to the rising edge of CK. (Identifier: MEM_DDR3_TIS_PS)
tIS (base) AC level tIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period. (Identifier: MEM_DDR3_TIS_AC_MV)
tIH (base) tIH (base) refers to the hold time for the Address/Command (A) bus after the rising edge of CK. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user chooses the "tIH (base) AC level"). (Identifier: MEM_DDR3_TIH_PS)
tIH (base) DC level tIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period. (Identifier: MEM_DDR3_TIH_DC_MV)
tDS (base) tDS(base) refers to the setup time for the Data(DQ) bus before the rising edge of the DQS strobe. (Identifier: MEM_DDR3_TDS_PS)
tDS (base) AC level tDS (base) AC level refers to the voltage level which the data bus must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period. (Identifier: MEM_DDR3_TDS_AC_MV)
tDH (base) tDH (base) refers to the hold time for the Data (DQ) bus after the rising edge of CK. (Identifier: MEM_DDR3_TDH_PS)
tDH (base) DC level tDH (base) DC level refers to the voltage level which the data bus must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period. (Identifier: MEM_DDR3_TDH_DC_MV)
tDQSQ tDQSQ describes the latest valid transition of the associated DQ pins for a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It is the length of time between the DQS, DQS# crossing to the last valid transition of the slowest DQ pin in the DQ group associated with that DQS strobe. (Identifier: MEM_DDR3_TDQSQ_PS)
tQH tQH specifies the output hold time for the DQ in relation to DQS, DQS#. It is the length of time between the DQS, DQS# crossing to the earliest invalid transition of the fastest DQ pin in the DQ group associated with that DQS strobe. (Identifier: MEM_DDR3_TQH_CYC)
tDQSCK tDQSCK describes the skew between the memory clock (CK) and the input data strobes (DQS) used for reads. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge. (Identifier: MEM_DDR3_TDQSCK_PS)
tDQSS tDQSS describes the skew between the memory clock (CK) and the output data strobes used for writes. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge. (Identifier: MEM_DDR3_TDQSS_CYC)
tQSH tQSH refers to the differential High Pulse Width, which is measured as a percentage of tCK. It is the time during which the DQS is high for a read. (Identifier: MEM_DDR3_TQSH_CYC)
tDSH tDSH specifies the write DQS hold time. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK. (Identifier: MEM_DDR3_TDSH_CYC)
tWLS tWLS describes the write leveling setup time. It is measured from the rising edge of CK to the rising edge of DQS. (Identifier: MEM_DDR3_TWLS_PS)
tWLH tWLH describes the write leveling hold time. It is measured from the rising edge of DQS to the rising edge of CK (Identifier: MEM_DDR3_TWLH_PS)
tDSS tDSS describes the time between the falling edge of DQS to the rising edge of the next CK transition. (Identifier: MEM_DDR3_TDSS_CYC)
tINIT tINIT describes the time duration of the memory initialization after a device power-up. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM starts internal initialization; this happens independently of external clocks. (Identifier: MEM_DDR3_TINIT_US)
tMRD The mode register set command cycle time, tMRD is the minimum time period required between two MRS commands. (Identifier: MEM_DDR3_TMRD_CK_CYC)
tRAS tRAS describes the activate to precharge duration. A row cannot be deactivated until the tRAS time has been met. Therefore tRAS determines how long the memory has to wait after a activate command before a precharge command can be issued to close the row. (Identifier: MEM_DDR3_TRAS_NS)
tRCD tRCD, row command delay, describes the active to read/write time. It is the amount of delay between the activation of a row through the RAS command and the access to the data through the CAS command. (Identifier: MEM_DDR3_TRCD_NS)
tRP tRP refers to the Precharge (PRE) command period. It describes how long it takes for the memory to disable access to a row by precharging and before it is ready to activate a different row. (Identifier: MEM_DDR3_TRP_NS)
tWR tWR refers to the Write Recovery time. It specifies the amount of clock cycles needed to complete a write before a precharge command can be issued. (Identifier: MEM_DDR3_TWR_NS)
Table 189.  Group: Mem Timing / Parameters dependent on Speed Bin, Operating Frequency, and Page Size
Display Name Description
tRRD tRRD refers to the Row Active to Row Active Delay. It is the minimum time interval (measured in memory clock cycles) between two activate commands to rows in different banks in the same rank (Identifier: MEM_DDR3_TRRD_CYC)
tFAW tFAW refers to the four activate window time. It describes the period of time during which only four banks can be active. (Identifier: MEM_DDR3_TFAW_NS)
tWTR tWTR or Write Timing Parameter describes the delay from start of internal write transaction to internal read command, for accesses to the same bank. The delay is measured from the first rising memory clock edge after the last write data is received to the rising memory clock edge when a read command is received. (Identifier: MEM_DDR3_TWTR_CYC)
tRTP tRTP refers to the internal READ Command to PRECHARGE Command delay. It is the number of memory clock cycles that is needed between a read command and a precharge command to the same rank. (Identifier: MEM_DDR3_TRTP_CYC)
Table 190.  Group: Mem Timing / Parameters dependent on Density and Temperature
Display Name Description
tRFC tRFC refers to the Refresh Cycle Time. It is the amount of delay after a refresh command before an activate command can be accepted by the memory. This parameter is dependent on the memory density and is necessary for proper hardware functionality. (Identifier: MEM_DDR3_TRFC_NS)
tREFI tREFI refers to the average periodic refresh interval. It is the maximum amount of time the memory can tolerate in between each refresh command (Identifier: MEM_DDR3_TREFI_US)

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