External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.7.2.2.3. Enabling the EMIF Unified Calibration Debug Toolkit in an Existing Design

To enable Unified Toolkit support in an existing design, follow these steps.
  1. Add the following line to the .qsf file: set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
  2. For each EMIF instance in the design, select Add EMIF Debug Interface from the Intel Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port drop-down menu.
  3. Click Generate HDL and compile the design.
Note: If your original EMIF IP version is older than 19.2.1, or if your design was not generated based on the design example, you must regenerate the design beginning with a design example. Follow the instructions in Generating a Design Example with the Debug Toolkit and in Adding Interfaces to an Design Example.

Did you find the information on this page useful?

Characters remaining:

Feedback Message