External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.5.2.1. Importance of Accurate Channel Signal Integrity Information

Default values for channel loss (or eye reduction) can be used when calculating timing margins, however those default values may not accurately reflect the channel loss in your system. If the channel loss in your system is different than the default values, the calculated timing margins vary accordingly.

If your actual channel loss is greater than the default channel loss, and if you rely on default values, the available timing margins for the entire system are lower than the values calculated during compilation. By relying on default values that do not accurately reflect your system, you may be lead to believe that you have good timing margin, while in reality, your design may require changes to achieve good channel signal integrity.

Did you find the information on this page useful?

Characters remaining:

Feedback Message