External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.4.19. sideband13

address=56(32 bit)

Field Bit High Bit Low Description Access
mr_cmd_opcode 31 0 Register Command Opcode. Information used for register command. Read/Write
DDR4
[26:24] C2:C0
[23] ACT
[22:21] BG1:BG0
[20] Reserved
[19:18] BA1:BA0
[17] A17
[16] RAS#
[15] CAS#
[14] WE#
[13:0] A13:A0
MRS: [22:21] is BG1:BG0, [19:18] is BA1:BA0, [13:0] is Opcode[13:0]
 
DDR3
[26:21] Reserved
[20:18] BA2:BA0
[17] A14
[16] RAS#
[15] CAS#
[14] WE#
[13:0] A13:A0
MRS: [19:18] is BA1:BA0, [13:0] is Opcode[13:0]

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