External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.7.2.7.10. Debugging VREFOUT Calibration Failure

  1. Ensure the address and command pins are connected correctly and that every calibrated pin has sufficient margin.
  2. Ensure that the VREFCA pins on the DDR memory component are powered up to 0.6V.