External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
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4.1.1.33. ctrl_mmr_slave for DDR3

Controller MMR slave interface

Table 44.  Interface: ctrl_mmr_slaveInterface type: Avalon Memory-Mapped Slave
Port Name Direction Description
mmr_slave_waitrequest Output Wait-request is asserted when controller MMR interface is busy
mmr_slave_read Input MMR read request signal
mmr_slave_write Input MMR write request signal
mmr_slave_address Input Word address for MMR interface of memory controller
mmr_slave_readdata Output MMR read data
mmr_slave_writedata Input MMR write data
mmr_slave_burstcount Input Number of transfers in each read/write burst
mmr_slave_beginbursttransfer Input Indicates when a burst is starting
mmr_slave_readdatavalid Output Indicates whether MMR read data is valid

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