External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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4.1.5.21. clks_sharing_slave_in for RLDRAM 3

Core clocks sharing slave input interface

Table 159.  Interface: clks_sharing_slave_inInterface type: Conduit
Port Name Direction Description
clks_sharing_slave_in Input This port should be connected to the core clocks sharing master.