External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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3.1.6. Intel® Stratix® 10 EMIF Architecture: Input DQS Clock Tree

The input DQS clock tree is a balanced clock network that distributes the read capture clock (such as CQ/CQ# or QK/QK# which are free-running read clocks) and strobe (such as DQS/DQS#) from the external memory device to the read capture registers inside the I/Os.

You can configure an input DQS clock tree in x4 mode, x8/x9 mode, x18 mode, or x36 mode.

Within every bank, only certain physical pins at specific locations can drive the input DQS clock trees. The pin locations that can drive the input DQS clock trees vary, depending on the size of the group.

Table 4.  Pins Usable as Read Capture Clock / Strobe Pair
Group Size Index of Lanes Spanned by Clock Tree In-Bank Index of Pins Usable as Read Capture Clock / Strobe Pair
Positive Leg Negative Leg
x4 0A 4 5
x4 0B 8 9
x4 1A 16 17
x4 1B 20 21
x4 2A 28 29
x4 2B 32 33
x4 3A 40 41
x4 3B 44 45
x8 / x9 0 4 5
x8 / x9 1 16 17
x8 / x9 2 28 29
x8 / x9 3 40 41
x18 0, 1 8 9
x18 2, 3 32 33
x36 0, 1, 2, 3 20 21

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