External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.4. caltiming0

address=31(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_act_to_rdwr 5 0 Activate to Read/Write command timing. Read
cfg_t_param_act_to_pch 11 6 Active to precharge. Read
cfg_t_param_act_to_act 17 12 Active to activate timing on same bank. Read
cfg_t_param_act_to_act_diff_bank 23 18 Active to activate timing on different banks, for DDR4 same bank group. Read
cfg_t_param_act_to_act_diff_bg 29 24 Active to activate timing on different bank groups, DDR4 only. Read

Did you find the information on this page useful?

Characters remaining:

Feedback Message