External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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12.4.5. Additive Latency and Bank Interleaving

Using additive latency together with bank interleaving increases the bandwidth of the controller.

The following figure shows an example of bank interleaving in a read operation without additive latency. The example uses bank interleave reads with CAS latency of  5, and burst length of  8.

Figure 105. Bank Interleaving—Without Additive Latency

Bank Interleaving—Without Additive Latency

The following sequence of events describes the above figure:

  1. The controller issues an activate command to open the bank, which activates bank x and the row in it.
  2. After tRCD time, the controller issues a read with auto-precharge command to the specified bank.
  3. Bank y receives an activate command after tRRD time.
  4. The controller cannot issue an activate command to bank z at its optimal location because it must wait for bank x to receive the read with auto‑precharge command, thus delaying the activate command for one clock cycle.
  5. The delay in activate command causes a gap in the output data from the memory device.
Note: If you use additive latency of 1, the latency affects only read commands and not the timing for write commands.

The following figure shows an example of bank interleaving in a read operation with additive latency. The example uses bank interleave reads with additive latency of 3, CAS latency of  5, and burst length of  8. In this configuration, the controller issues back-to-back activate and read with auto-precharge commands.

Figure 106. Bank Interleaving—With Additive Latency

Bank Interleaving—With Additive Latency

The following sequence of events describes the above figure:

  1. The controller issues an activate command to bank x.
  2. The controller issues a read with auto precharge command to bank x right after the activate command, before waiting for the tRCD time.
  3. The controller executes the read with auto-precharge command tRCD time later on the rising edge T4.
  4. 5 cycles of CAS latency later, the SDRAM device issues the data on the data bus.
  5. For burst length of 8, you need 2 cycles for data transfer. With 2 clocks of giving activate and read with auto-precharge commands, you get a continuous flow of output data.

Compare the efficiency results in the two preceding figures:

  • bank interleave reads with no additive latency, CAS latency of 5, and burst length of 8 (first figure),

    Number of active cycles of data transfer = 8.

    Total number of cycles = 18

    Efficiency = 44%

  • bank interleave reads with additive latency of 3, CAS latency of 4, and burst length of 4 (second figure),

    Number of active cycles of data transfer = 8.

    Total number of cycles = 17

    Efficiency = approximately 47%

The interleaving reads used with additive latency increases efficiency by approximately 3%.

Note: Additive latency improves the efficiency of back-to-back interleaved reads or writes, but not individual random reads or writes.

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