10.3.1.6.2. RLDRAM 3 Commands and Addresses
These pins operate at single data rate using only one clock edge. RLDRAM 3 supports both non-multiplexed and multiplexed addressing. Multiplexed addressing allows you to save a few user I/O pins while non‑multiplexed addressing allows you to send the address signal within one clock cycle instead of two clock cycles. CS#, REF#, and WE# pins are input commands to the RLDRAM 3 device.
The commands and addresses must meet the memory address and command setup (tAS, tCS) and hold (tAH, tCH) time requirements.
Did you find the information on this page useful?