External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Document Table of Contents RLDRAM 3 Commands and Addresses

The CK and CK# signals clock the commands and addresses into the memory devices.

These pins operate at single data rate using only one clock edge. RLDRAM 3 supports both non-multiplexed and multiplexed addressing. Multiplexed addressing allows you to save a few user I/O pins while non‑multiplexed addressing allows you to send the address signal within one clock cycle instead of two clock cycles. CS#, REF#, and WE# pins are input commands to the RLDRAM 3 device.

The commands and addresses must meet the memory address and command setup (tAS, tCS) and hold (tAH, tCH) time requirements.

Note: The RLDRAM 3 external memory interface IP does not support multiplexed addressing.

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