3.1.4. Intel® Stratix® 10 EMIF Architecture: I/O Bank
Each I/O bank resides in an I/O column, and contains the following components:
- Hard memory controller
- Sequencer components
- PLL and PHY clock trees
- Input DQS clock trees
- 48 pins, organized into four I/O lanes of 12 pins each
I/O Bank Usage
The pins in an I/O bank can serve as address and command pins, data pins, or clock and strobe pins for an external memory interface. You can implement a narrow interface, such as a DDR3 or DDR4 x8 interface, with only a single I/O bank. A wider interface of up to 72 bits can be implemented by configuring multiple adjacent banks in a multi-bank interface. Any pins in a bank which are not used by the EMIF IP can serve as general-purpose I/O pins of uncalibrated I/O standard with the same voltage settings.
Every I/O bank includes a hard memory controller which you can configure for DDR3 or DDR4. In a multi-bank interface, only the controller of one bank is active; controllers in the remaining banks are turned off to conserve power.
To use a multi-bank Intel® Stratix® 10 EMIF interface, you must observe the following rules:
- Designate one bank as the address and command bank.
- The address and command bank must contain all the address and command pins.
- The locations of individual address and command pins within the address and command bank must adhere to the pin map defined in the pin table— regardless of whether you use the hard memory controller or not.
- If you do use the hard memory controller, the address and command bank contains the active hard controller.
All the I/O banks in a column are capable of functioning as the address and command bank. However, for minimal latency, you should select the center-most bank of the interface as the address and command bank.
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