External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.1.2.18. emif_usr_clk for DDR4

User clock interface

Table 66.  Interface: emif_usr_clkInterface type: Clock Output
Port Name Direction Description
emif_usr_clk Output User clock domain

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