External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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Document Table of Contents

15. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.03.11 21.3 19.2.4 In the Debugging Intel® Stratix® 10 EMIF IP section of the Debugging chapter, added Guidelines for Debugging Calibration Issues section.
2021.12.06 21.3 19.2.4
  • Removed the Multiple Interfaces in the Same I/O Column paragraph from the General Guidelines topic in the Pin Guidelines section of each protocol-specific chapter.
  • In the DDR4 chapter:
    • Added the alert_n Pin Termination Recommendation topic to the Pin Guidelines section.
    • Modified the alert_n pin termination recommendation in the Length Matching Rules topic.
2021.10.04 21.3 19.2.4
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR3 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the DDR4 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the Debugging chapter:
    • Updated the Configuration and Status Registers table.
    • Updated the Address Pattern topic.
    • Updated the Address Pattern topic and added several new topics:
      • Address Generator Modes
      • Address Generator MSB Indices
      • Address Generator Effective Width
      • Address Generator Relative Frequencies
      • Address Pattern Examples - Basic Mode
      • Address Pattern Examples - Advanced Mode
    • Updated the Error Codes table.
    • In the Configuring the Traffic Generator topic, updated the Configurations Tab figure, and added several figures:
      • Instruction Pattern tab: Separate Read and Write Settings
      • Address Pattern Tab – Basic Mode
      • Address Pattern Tab – Advanced Mode
      • Address Pattern tab: Separate Read and Write Settings – Basic Mode
      • Address Pattern tab: Separate Read and Write Settings – Advanced Mode
2021.07.09 21.2 19.2.4 In the Debugging chapter, modified the Code Value column, and added one row, to the Error Codes table in the Traffic Generator Status topic. .
2021.06.21 21.2 19.2.4
  • In the Simulation chapter, added information to the Skip Calibration Mode description in the Calibration Modes topic.
  • In the Debugging chapter, added the Examples of Configuring the TG2 Traffic Generator topic in the Using the Configurable Traffic Generator (TG2) section.
2021.03.29 21.1 19.2.3
  • In the Simulating Memory IP chapter, removed references to the NCSim* simulator.
  • In the Intel® Stratix® 10 EMIF IP DDR4 chapter, added content to the Enable ALERT#/PAR pins description, in the Intel® Stratix® 10 EMIF IP DDR4 Parameters: Memory topic.
  • Added Package Migration topic to the Board Design Guidelines section of each protocol-specific chapter.
2020.12.18 20.4 19.2.2
  • In the Simulation chapter, added a paragraph to the Simulation Walkthrough topic.
  • In the Debugging chapter, removed the Using the Traffic Generator with the Generated Design Example topic, and added the Using the Default Traffic Generator and Using the Configurable Traffic Generator (TG2) sections.
2020.10.05 20.3 19.2.2
  • In the Introduction chapter, updated the Release Information topic.
  • In the MMR Tables section of the End-User Signals chapter, added ECC error information to the ecc6: Address of Most Recent Correction Command Dropped topic.
  • In the Debugging chapter, renamed the existing EMIF Debug Toolkit as the Legacy EMIF Debug Toolkit.
  • In the Unified Calibration Debug Toolkit section of the Debugging chapter, modified the following topics:
    • Adding Interfaces to a Design Example (updated images)
    • Calibration Tab (updated images and added section on changing address ordering)
    • Calibration Report Tab (added ODT Settings in Effect section, modified Calibration Status Report section, and added Address and Command Calibration Delays and Margins section)
    • Calibrate Termination Tab (recast text, updated images, added ODT Assertion Table section)
    • ISSP Tab (added PRTY description to Table 351)
    • Viewing Diagrams in the Eye Viewer (added a fourth eye diagram)
  • In the Legacy Efficiency Monitor and Protocol Checker section, made minor changes to several topics to differentiate between the legacy efficiency monitor and the new efficiency monitor.
  • Added the New Efficiency Monitor section, consisting of the following topics:
    • New Efficiency Monitor
    • Enabling the Efficiency Monitor in a Design Example
    • Efficiency Monitor Block Descriptions
    • Control and Status Registers
    • Opening the Efficiency Monitor
2020.06.22 20.2 19.2.1
  • In the Functional Simulation chapter, added a third note to the Abstract PHY Simulation topic.
  • In the Debugging chapter:
    • Added content to the Debugging Intel® Stratix® 10 EMIF IP topic.
    • Added the Debugging with the External Memory Interface Unified Calibration Debug Toolkit section.
2020.04.30 20.1 19.2.0
  • In the Interface and Signal Descriptions chapter, added ctrl_ecc_status_for DDR3 and ctrl_ecc_status_for_DDR4 topics.
2020.04.10 19.3 19.1.0
  • In the Product Architecture chapter, changed the second figure and step 4, in the Restrictions on I/O Bank Usage for Intel® Stratix® 10 EMIF IP with HPS topic.
  • In the Product Architecture and Simulating chapters, added the HPS EMIF Simulation topic.
  • In the Controller Parameters section of the DDR3 and DDR4 chapters, removed a sentence from the description of the Enable Error Detection and Correction Logic with ECC parameter.
  • In the Equations for QDR-IV Board Skew Parameters section of the Intel® Stratix® 10 EMIF IP for QDR-IV chapter, implemented a correction to the equation in the description of the Average delay difference between DK and CK parameter.
2020.01.27 19.3 19.1.0
  • In the Intel® Stratix® 10 EMIF IP for DDR3 chapter:
    • In the Parameter Descriptions section, removed four parameter descriptions from the Group: Diagnostics / Simulation Options table.
    • Added the x4 DIMM Implementation topic in the Pin Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP for DDR4 chapter:
    • Removed four parameter descriptions from the Group: Diagnostics / Simulation Options table in the Parameter Descriptions section.
    • Added the x4 DIMM Implementation topic in the Pin Guidelines section.
    • Minor rewording and additions to the Clamshell Topology topic in the Board Design Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP Debugging chapter, implemented a minor rewording of the last bullet point in the Intermittent Issue Evaluation topic.
2019.09.30 19.3 19.1.0
  • Added the Release Information topic.
  • In the Product Architecture chapter:
    • In the Intel® Stratix® 10 EMIF Architecture: I/O SSM topic, updated the two figures.
    • Added a note about restrictions on I/O bank usage for EMIF on certain devices to the I/O Column and I/O Bank topics.
    • Added note to the Intel® Stratix® 10 EMIF for Hard Processor Subsystem topic.
  • In the Intel® Stratix® 10 EMIF IP End-User Signals chapter:
    • Expanded the description of the mem_a port in the mem for DDR4 topic in the Intel® Stratix® 10 EMIF IP Interfaces for DDR4 section.
    • Removed sideband2, sideband3, sideband5, sideband8, and sideband10 from the Memory Mapped Register (MMR) Tables section.
  • In each of the protocol-specific chapters, changed the wording of the first paragraph in the Interface Pins topic to emphasize the importance of always referring to the device pin table and EMIF pin table to determine correct pin locations.
  • In the Intel® Stratix® 10 EMIF IP for DDR3 chapter:
    • Changed the text of the third bullet in step 10, in the General Guidelines topic of the Pin Guidelines section.
    • In the Board Design Guidelines topic, added information on I/O standards.
  • In the Intel® Stratix® 10 EMIF IP for DDR4 chapter:
    • Added Additional Layout Guidelines for DDR4 Twin-die Devices topic to the DDR4 Board Design Guidelines section.
    • In the Board Design Guidelines topic, added information on I/O standards.
    • Changed the text of the third bullet in step 10, in the General Guidelines topic of the Pin Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP Debugging chapter:
    • Restructured the Debugging Intel® Stratix® 10 EMIF IP section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
  • Added the User Guide Archives chapter.
2019.04.01 19.1  
  • Added Slew Rates topic to the Board Design Guidelines section in each of the DDR3, DDR4, QDR II/II+/II+ Xtreme, QDR-IV, and RLDRAM 3 protocol-specific chapters.
  • Revised the Optimizing Timing topic in the Intel® Stratix® 10 EMIF IP Timing Closure chapter.
2018.12.24 18.1.1  
  • Added the Clamshell Topology topic to the DDR4 Board Design Guidelines subsection of the Intel® Stratix® 10 EMIF IP for DDR4 chapter.
2018.12.06 18.1  
  • Modified the In-bank Index numbers for the x18 rows of the Pins Usable as Read Capture Clock / Strobe Pair table in the Intel Stratix 10 EMIF Architecture: Input DQS Clock Tree topic in the Intel® Stratix® 10 EMIF IP Product Architecture chapter.
2018.12.03 18.1  
  • Modified the Restrictions on I/O Bank Usage for Intel® Stratix® 10 EMIF IP with HPS topic in the Intel® Stratix® 10 EMIF for Hard Processor Subsystem section of the Intel® Stratix® 10 EMIF IP Product Architecture chapter.
2018.09.24 18.1