External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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Document Table of Contents

15. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.03.11 21.3 19.2.4 In the Debugging Intel® Stratix® 10 EMIF IP section of the Debugging chapter, added Guidelines for Debugging Calibration Issues section.
2021.12.06 21.3 19.2.4
  • Removed the Multiple Interfaces in the Same I/O Column paragraph from the General Guidelines topic in the Pin Guidelines section of each protocol-specific chapter.
  • In the DDR4 chapter:
    • Added the alert_n Pin Termination Recommendation topic to the Pin Guidelines section.
    • Modified the alert_n pin termination recommendation in the Length Matching Rules topic.
2021.10.04 21.3 19.2.4
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR3 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the DDR4 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the Debugging chapter:
    • Updated the Configuration and Status Registers table.
    • Updated the Address Pattern topic.
    • Updated the Address Pattern topic and added several new topics:
      • Address Generator Modes
      • Address Generator MSB Indices
      • Address Generator Effective Width
      • Address Generator Relative Frequencies
      • Address Pattern Examples - Basic Mode
      • Address Pattern Examples - Advanced Mode
    • Updated the Error Codes table.
    • In the Configuring the Traffic Generator topic, updated the Configurations Tab figure, and added several figures:
      • Instruction Pattern tab: Separate Read and Write Settings
      • Address Pattern Tab – Basic Mode
      • Address Pattern Tab – Advanced Mode
      • Address Pattern tab: Separate Read and Write Settings – Basic Mode
      • Address Pattern tab: Separate Read and Write Settings – Advanced Mode
2021.07.09 21.2 19.2.4 In the Debugging chapter, modified the Code Value column, and added one row, to the Error Codes table in the Traffic Generator Status topic. .
2021.06.21 21.2 19.2.4
  • In the Simulation chapter, added information to the Skip Calibration Mode description in the Calibration Modes topic.
  • In the Debugging chapter, added the Examples of Configuring the TG2 Traffic Generator topic in the Using the Configurable Traffic Generator (TG2) section.
2021.03.29 21.1 19.2.3
  • In the Simulating Memory IP chapter, removed references to the NCSim* simulator.
  • In the Intel® Stratix® 10 EMIF IP DDR4 chapter, added content to the Enable ALERT#/PAR pins description, in the Intel® Stratix® 10 EMIF IP DDR4 Parameters: Memory topic.
  • Added Package Migration topic to the Board Design Guidelines section of each protocol-specific chapter.
2020.12.18 20.4 19.2.2
  • In the Simulation chapter, added a paragraph to the Simulation Walkthrough topic.
  • In the Debugging chapter, removed the Using the Traffic Generator with the Generated Design Example topic, and added the Using the Default Traffic Generator and Using the Configurable Traffic Generator (TG2) sections.
2020.10.05 20.3 19.2.2
  • In the Introduction chapter, updated the Release Information topic.
  • In the MMR Tables section of the End-User Signals chapter, added ECC error information to the ecc6: Address of Most Recent Correction Command Dropped topic.
  • In the Debugging chapter, renamed the existing EMIF Debug Toolkit as the Legacy EMIF Debug Toolkit.
  • In the Unified Calibration Debug Toolkit section of the Debugging chapter, modified the following topics:
    • Adding Interfaces to a Design Example (updated images)
    • Calibration Tab (updated images and added section on changing address ordering)
    • Calibration Report Tab (added ODT Settings in Effect section, modified Calibration Status Report section, and added Address and Command Calibration Delays and Margins section)
    • Calibrate Termination Tab (recast text, updated images, added ODT Assertion Table section)
    • ISSP Tab (added PRTY description to Table 351)
    • Viewing Diagrams in the Eye Viewer (added a fourth eye diagram)
  • In the Legacy Efficiency Monitor and Protocol Checker section, made minor changes to several topics to differentiate between the legacy efficiency monitor and the new efficiency monitor.
  • Added the New Efficiency Monitor section, consisting of the following topics:
    • New Efficiency Monitor
    • Enabling the Efficiency Monitor in a Design Example
    • Efficiency Monitor Block Descriptions
    • Control and Status Registers
    • Opening the Efficiency Monitor
2020.06.22 20.2 19.2.1
  • In the Functional Simulation chapter, added a third note to the Abstract PHY Simulation topic.
  • In the Debugging chapter:
    • Added content to the Debugging Intel® Stratix® 10 EMIF IP topic.
    • Added the Debugging with the External Memory Interface Unified Calibration Debug Toolkit section.
2020.04.30 20.1 19.2.0
  • In the Interface and Signal Descriptions chapter, added ctrl_ecc_status_for DDR3 and ctrl_ecc_status_for_DDR4 topics.
2020.04.10 19.3 19.1.0
  • In the Product Architecture chapter, changed the second figure and step 4, in the Restrictions on I/O Bank Usage for Intel® Stratix® 10 EMIF IP with HPS topic.
  • In the Product Architecture and Simulating chapters, added the HPS EMIF Simulation topic.
  • In the Controller Parameters section of the DDR3 and DDR4 chapters, removed a sentence from the description of the Enable Error Detection and Correction Logic with ECC parameter.
  • In the Equations for QDR-IV Board Skew Parameters section of the Intel® Stratix® 10 EMIF IP for QDR-IV chapter, implemented a correction to the equation in the description of the Average delay difference between DK and CK parameter.
2020.01.27 19.3 19.1.0
  • In the Intel® Stratix® 10 EMIF IP for DDR3 chapter:
    • In the Parameter Descriptions section, removed four parameter descriptions from the Group: Diagnostics / Simulation Options table.
    • Added the x4 DIMM Implementation topic in the Pin Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP for DDR4 chapter:
    • Removed four parameter descriptions from the Group: Diagnostics / Simulation Options table in the Parameter Descriptions section.
    • Added the x4 DIMM Implementation topic in the Pin Guidelines section.
    • Minor rewording and additions to the Clamshell Topology topic in the Board Design Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP Debugging chapter, implemented a minor rewording of the last bullet point in the Intermittent Issue Evaluation topic.
2019.09.30 19.3 19.1.0
  • Added the Release Information topic.
  • In the Product Architecture chapter:
    • In the Intel® Stratix® 10 EMIF Architecture: I/O SSM topic, updated the two figures.
    • Added a note about restrictions on I/O bank usage for EMIF on certain devices to the I/O Column and I/O Bank topics.
    • Added note to the Intel® Stratix® 10 EMIF for Hard Processor Subsystem topic.
  • In the Intel® Stratix® 10 EMIF IP End-User Signals chapter:
    • Expanded the description of the mem_a port in the mem for DDR4 topic in the Intel® Stratix® 10 EMIF IP Interfaces for DDR4 section.
    • Removed sideband2, sideband3, sideband5, sideband8, and sideband10 from the Memory Mapped Register (MMR) Tables section.
  • In each of the protocol-specific chapters, changed the wording of the first paragraph in the Interface Pins topic to emphasize the importance of always referring to the device pin table and EMIF pin table to determine correct pin locations.
  • In the Intel® Stratix® 10 EMIF IP for DDR3 chapter:
    • Changed the text of the third bullet in step 10, in the General Guidelines topic of the Pin Guidelines section.
    • In the Board Design Guidelines topic, added information on I/O standards.
  • In the Intel® Stratix® 10 EMIF IP for DDR4 chapter:
    • Added Additional Layout Guidelines for DDR4 Twin-die Devices topic to the DDR4 Board Design Guidelines section.
    • In the Board Design Guidelines topic, added information on I/O standards.
    • Changed the text of the third bullet in step 10, in the General Guidelines topic of the Pin Guidelines section.
  • In the Intel® Stratix® 10 EMIF IP Debugging chapter:
    • Restructured the Debugging Intel® Stratix® 10 EMIF IP section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
  • Added the User Guide Archives chapter.
2019.04.01 19.1  
  • Added Slew Rates topic to the Board Design Guidelines section in each of the DDR3, DDR4, QDR II/II+/II+ Xtreme, QDR-IV, and RLDRAM 3 protocol-specific chapters.
  • Revised the Optimizing Timing topic in the Intel® Stratix® 10 EMIF IP Timing Closure chapter.
2018.12.24 18.1.1  
  • Added the Clamshell Topology topic to the DDR4 Board Design Guidelines subsection of the Intel® Stratix® 10 EMIF IP for DDR4 chapter.
2018.12.06 18.1  
  • Modified the In-bank Index numbers for the x18 rows of the Pins Usable as Read Capture Clock / Strobe Pair table in the Intel Stratix 10 EMIF Architecture: Input DQS Clock Tree topic in the Intel® Stratix® 10 EMIF IP Product Architecture chapter.
2018.12.03 18.1  
  • Modified the Restrictions on I/O Bank Usage for Intel® Stratix® 10 EMIF IP with HPS topic in the Intel® Stratix® 10 EMIF for Hard Processor Subsystem section of the Intel® Stratix® 10 EMIF IP Product Architecture chapter.
2018.09.24 18.1  
  • Removed hps_emif from the QDR II, QDR-IV, and RLDRAM 3 sections in the Interface and Signal Descriptions section of the Intel® Stratix® 10 EMIF IP End-User Signals chapter.
  • Removed mem_ck, mem_ck_n, and mem_reset_n from the description of the mem interface for QDR II in the Interface and Signal Descriptions section of the Intel® Stratix® 10 EMIF IP End-User Signals chapter.
  • Removed a note from the I/O SSM Sharing topic, in the Product Architecture chapter.
  • Added notes to the Bank Management Efficiency and Data Transfer topics in the Optimizing Controller Performance chapter.
  • Modified the names of the interleaving options in the Bank Interleaving topic in the Optimizing Controller Performance chapter.
  • In the IP Debugging chapter, expanded the daisy chaining information in the Configuring Your EMIF IP for Use with the Debug Toolkit, Establishing Communication to Connections, and Selecting an Active interface topics.
  • Added Efficiency Monitor and Protocol Checker section to the IP Debugging chapter.
2018.08.08 18.0  
  • In the Command and Address Signals topic in the DDR3 and DDR4 chapters, changed SSTL-12 I/O standard reference to 1.2V I/O standard.
  • Modified the descriptions of the Clock rate of user logic, Memory format, DQ width, and Enable In-System-Sources-and-Probes parameters in the DDR3, DDR4, QDR II/II+/Xtreme, QDR-IV, and RLDRAM 3 chapters, as appropriate.
  • Removed the Traffic Generator 2.0 section from the Intel® Stratix® 10 EMIF IP Debugging chapter.
2018.05.07 18.0  
  • Changed document title from Intel® Stratix® 10 External Memory Interfaces IP User Guide to External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide.
  • In the Product Architecture chapter:
    • Revised the first paragraph of the Input DQS Clock Tree topic.
    • Modified statement about unused I/O pins in I/O Bank Usage and I/O Bank Sharing topics.
    • Added Hard Memory Controller, Hard Memory Controller Features, Hard Memory Controller Main Control Path, and Data Buffer Controller topics.
    • Added note to the I/O SSM Sharing topic, concerning possible calibration failure.
    • Removed all references to LPDDR3.
  • In the End-User Signals chapter:
    • Removed Intel® Stratix® 10 EMIF IP Interfaces for LPDDR3 section.
    • Removed all other references to LPDDR3.
  • In the Simulating Memory IP chapter:
    • Minor modifications to the Simulating Memory IP topic.
    • Minor modifications to the Simulation Walkthrough topic.
    • Changed directory path information in the Simulation Scripts, Functional Simulation with Verilog HDL, Functional Simulation with VHDL, and Simulating the Example Design topics.
  • In the DDR3 chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Stratix® 10 EMIF IP topic.
    • Added explanation of adjacent I/O banks to the I/O Banks Selection section in the General Guidelines topic.
    • Modified equations in Guidelines for Calculating DDR3 Channel Signal Integrity topic.
    • Removed all references to LPDDR3.
  • In the DDR4 chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Stratix® 10 EMIF IP topic.
    • In the General Guidelines topic, added guideline 14, describing I/O bank usage for DDR4 interfaces at 1333 MHz.
    • Added explanation of adjacent I/O banks to the I/O Banks Selection section in the General Guidelines topic.
    • Modified equations in Guidelines for Calculating DDR4 Channel Signal Integrity topic.
    • Removed all references to LPDDR3.
  • In the QDR II/II+/II+ Xtreme chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Stratix® 10 EMIF IP topic.
    • Removed all references to LPDDR3.
  • In the QDR-IV chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Stratix® 10 EMIF IP topic.
    • Removed all references to LPDDR3.
  • In the RLDRAM 3 chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Stratix® 10 EMIF IP topic.
    • Removed all references to LPDDR3.
  • Removed the LPDDR3 chapter.
  • In the Timing Closure chapter:
    • Updated figures in the Read Capture Timing Analysis, Write Timing Analysis, Address and Command Timing Analysis, DQS Gating Timing Analysis, Write Leveling Timing Analysis, and Timing Report DDR topics.
  • In the Optimizing Controller Performance chapter:
    • Revised the calculations in the Refresh bullet point in the Interface Standard topic.
    • Revised the Frequency of Operation topic.
    • Revised the Bandwidth equation in the Bandwidth topic.
    • Revised the bulleted list of tools and methods in the Improving Controller Efficiency topic.
    • Removed the Command Queue Look Ahead Depth topic.
    • Updated figure in Additive Latency topic.
    • Updated both figures and associated text in Additive Latency and Bank Interleaving topic.
    • Added sentence to the introductory paragraph of the Command Reordering topic.
    • Added Enable Command Priority Control topic.
    • Removed all references to LPDDR3.
Date Version Changes
November 2017 2017.11.06
  • Entire document extensively restructured and revised, consolidating relevant content from the External Memory Interface Handbook.
  • Created End-User Signals chapter, comprising interface and signal descriptions, AFI signals and timing diagrams, and memory-mapped register (MMR) information.
  • Created protocol-specific chapters consolidating parameter descriptions, board skew equations, pin planning information, and board design guidelines for each memory protocol.
  • Created chapters for Timing Closure, Optimizing Controller Performance, and Debugging.
May 2017 2017.05.08
  • Updated the topics in the I/O Column section.
  • Updated DQ and DQS Pins Assignment section with new pin information.
  • Updated the Placement Guidelines section with more detailed description.
  • Updated the Resource Sharing Guidelines for Intel® Stratix® 10EMIF IP section.
  • Updated the Parameterizing Intel® Stratix® 10 External Memory Interface IP section.
  • Updated the Parameterizing Altera PHYLite for Parallel Interfaces IP Core section.
  • Added a topic about OCT in the Altera PHYLite for Parallel Interfaces IP Core References section.
  • Added a note that you can only use the Report DDR function if you enable the dynamic reconfiguration feature. The dynamic reconfiguration feature is not available with the current version of the Altera PHYLite for Parallel Interfaces IP core.
October 2016 2016.10.31
  • Initial release.

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