External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
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4.4. Intel® Stratix® 10 Memory Mapped Register (MMR) Tables

The address buses to read and write from the MMR registers are 10 bits wide, while the read and write data buses are configured to be 32 bits. The Bits Register Link column in the table below provides the mapping on the width of the data read within the 32-bit bus. The reads and writes are always performed using the 32-bit-wide bus.

Register Summary

Register Address 32-bit Bus Bits Register Link
ctrlcfg0 10 32
ctrlcfg1 11 32
dramtiming0 20 32
caltiming0 31 32
caltiming1 32 32
caltiming2 33 32
caltiming3 34 32
caltiming4 35 32
caltiming9 40 32
dramaddrw 42 32
sideband0 43 32
sideband1 44 32
sideband4 47 32
sideband6 49 32
sideband7 50 32
sideband9 52 32
sideband11 54 32
sideband12 55 32
sideband13 56 32
sideband14 57 32
dramsts 59 32
niosreserve0 68 32
niosreserve1 69 32
sideband16 79 32
ecc3 130 32
ecc4 144 32
ecc5 145 32
ecc6 146 32
ecc7 147 32
ecc8 148 32
Note: Addresses are in decimal format.

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