External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.8.3. Changing the Reset Trigger of the Default Traffic Generator

As generated, the design example project responds to an active-high reset pulse on the local_reset_req signal.

If you prefer to have a level-sensitive, typically active-low reset signal as was common with earlier device families, you can invert the design example reset signal by making the following RTL changes to the ed_synth.v file:

  • Add the following two lines in the wire declaration section:
    wire reset_invert;
    assign reset_invert = !local_reset_req;
    
  • Where the reset block is instantiated, change the local_reset_req to connect to the inverted reset signal called reset_invert, as follows:
    ed_synth_local_reset_combiner local_reset_combiner (
    .clk
    (emif_fm0_0_pll_ref_clk_out_clk),
    .reset_n
    (emif_fm0_0_pll_locked_pll_locked),
    .local_reset_req
    (local_reset_req),
    .local_reset_req
    (reset_invert),
    .local_reset_req_out_0
    (local_reset_combiner_local_reset_req_out_0_local_reset_req),
    .local_reset_done
    (local_reset_done),
    .local_reset_done_in_0
    (emif_fm0_0_local_reset_status_local_reset_done)
    );

In addition, it is a good idea — though not mandatory — to also run analysis and elaboration, to help show project structure and verify assignments.

Did you find the information on this page useful?

Characters remaining:

Feedback Message