External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.3. Intel Stratix 10 EMIF IP DDR3 Parameters: Memory

Table 183.  Group: Memory / Topology
Display Name Description
Memory format Specifies the format of the external memory device. The following formats are supported: Component - a Discrete memory device; UDIMM - Unregistered/Unbuffered DIMM where address/control, clock, and data are unbuffered; RDIMM - Registered DIMM where address/control and clock are buffered; SODIMM - Small Outline DIMM is similar to UDIMM but smaller in size and is typically used for systems with limited space. Some memory protocols may not be available in all formats. (Identifier: MEM_DDR3_FORMAT_ENUM)
DQ width Specifies the total number of data pins in the interface. (Identifier: MEM_DDR3_DQ_WIDTH)
DQ pins per DQS group Specifies the total number of DQ pins per DQS group. (Identifier: MEM_DDR3_DQ_PER_DQS)
Number of clocks Specifies the number of CK/CK# clock pairs exposed by the memory interface. Usually more than 1 pair is required for RDIMM/LRDIMM formats. The value of this parameter depends on the memory device selected; refer to the data sheet for your memory device. (Identifier: MEM_DDR3_CK_WIDTH)
Number of chip selects Specifies the total number of chip selects in the interface, up to a maximum of 4. This parameter applies to discrete components only. (Identifier: MEM_DDR3_DISCRETE_CS_WIDTH)
Number of DIMMs Total number of DIMMs. (Identifier: MEM_DDR3_NUM_OF_DIMMS)
Number of physical ranks per DIMM Number of ranks per DIMM. For LRDIMM, this represents the number of physical ranks on the DIMM behind the memory buffer (Identifier: MEM_DDR3_RANKS_PER_DIMM)
Row address width Specifies the number of row address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available rows. (Identifier: MEM_DDR3_ROW_ADDR_WIDTH)
Column address width Specifies the number of column address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available columns. (Identifier: MEM_DDR3_COL_ADDR_WIDTH)
Bank address width Specifies the number of bank address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank address pins needed for access to all available banks. (Identifier: MEM_DDR3_BANK_ADDR_WIDTH)
Enable DM pins Indicates whether the interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group. (Identifier: MEM_DDR3_DM_EN)
Enable address mirroring for odd chip-selects Enabling address mirroring for multi-CS discrete components. Typically used when components are arranged in a clamshell layout. (Identifier: MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN)
Enable address mirroring for odd ranks Enabling address mirroring for dual-rank or quad-rank DIMM. (Identifier: MEM_DDR3_MIRROR_ADDRESSING_EN)
ALERT# pin placement Specifies placement for the mem_alert_n signal. You can select "I/O Lane with Address/Command Pins" or "I/O Lane with DQS Group". If you select "I/O Lane with DQS Group", you can specify the DQS group with which to place the mem_alert_n pin. For optimum signal integrity, you should choose "I/O Lane with Address/Command Pins". For interfaces containing multiple memory devices, it is recommended to connect the ALERT# pins together to the ALERT# pin on the FPGA. (Identifier: MEM_DDR3_ALERT_N_PLACEMENT_ENUM)
DQS group of ALERT# Select the DQS group with which the ALERT# pin is placed. (Identifier: MEM_DDR3_ALERT_N_DQS_GROUP)
Table 184.  Group: Memory / Latency and Burst
Display Name Description
Memory CAS latency setting Specifies the number of clock cycles between the read command and the availability of the first bit of output data at the memory device. Overall read latency equals the additive latency (AL) + the CAS latency (CL). Overall read latency depends on the memory device selected; refer to the datasheet for your device. (Identifier: MEM_DDR3_TCL)
Memory write CAS latency setting Specifies the number of clock cycles from the release of internal write to the latching of the first data in at the memory device. This value depends on the memory device selected; refer to the datasheet for your device. (Identifier: MEM_DDR3_WTCL)
Memory additive CAS latency setting Determines the posted CAS additive latency of the memory device. Enable this feature to improve command and bus efficiency, and increase system bandwidth. (Identifier: MEM_DDR3_ATCL_ENUM)
Table 185.  Group: Memory / Mode Register Settings
Display Name Description
Hide advanced mode register settings Show or hide advanced mode register settings. Changing advanced mode register settings to non-default values is strongly discouraged. (Identifier: MEM_DDR3_HIDE_ADV_MR_SETTINGS)
Burst Length Specifies the DRAM burst length which determines how many consecutive addresses should be accessed for a given read/write command. (Identifier: MEM_DDR3_BL_ENUM)
Read Burst Type Indicates whether accesses within a given burst are in sequential or interleaved order. Select sequential if you are using the Intel-provided memory controller. (Identifier: MEM_DDR3_BT_ENUM)
DLL precharge power down Specifies whether the DLL in the memory device is off or on during precharge power-down (Identifier: MEM_DDR3_PD_ENUM)
Enable the DLL in memory device Enable the DLL in memory device (Identifier: MEM_DDR3_DLL_EN)
Auto self-refresh method Indicates whether to enable or disable auto self-refresh. Auto self-refresh allows the controller to issue self-refresh requests, rather than manually issuing self-refresh in order for memory to retain data. (Identifier: MEM_DDR3_ASR_ENUM)
Self-refresh temperature Specifies the self-refresh temperature as "Normal" or "Extended" mode. More information on Normal and Extended temperature modes can be found in the memory device datasheet. (Identifier: MEM_DDR3_SRT_ENUM)
DDR3 RDIMM/LRDIMM control words Each 4-bit/8-bit setting can be obtained from the manufacturer's data sheet and should be entered in hexadecimal, starting with the 8-bit setting RCBx on the left and continuing to RC1x followed by the 4-bit setting RCOF and ending with RC00 on the right (Identifier: MEM_DDR3_RDIMM_CONFIG)
DDR3 LRDIMM additional control words Each 4-bit setting can be obtained from the manufacturer's data sheet and should be entered in hexadecimal, starting with BC0F on the left and ending with BC00 on the right (Identifier: MEM_DDR3_LRDIMM_EXTENDED_CONFIG)

Did you find the information on this page useful?

Characters remaining:

Feedback Message